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Part Number: HDD64M72D18RPW

 

 

 

 

Description: The HDD64M72D18RPW is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory...


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HDD64M72D18RPW General Description


The HDD64M72D18RPW is a 64M x 72 bit Double Data Rate(DDR) Synchronous Dynamic RAM high-density memory module. The module consists of eighteen CMOS 32M x 8 bit with 4banks DDR SDRAMs in 66pin TSOP-II 400mil packages and 2K EEPROM in 8-pin TSSOP package on a 184-pin glass-epoxy. Four 0.1uF decoupling capacitors are mounted on the printed circuit board in parallel for each DDR SDRAM. The HDD64M72D18RPW is a DIMM( Dual in line Memory Module) .Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allows the same device to be useful for a variety of high bandwidth, high performance memory system applications. All module components may be powered from a single 2.5V DC power supply and all inputs and outputs are SSTL_2 compatible.

HDD64M72D18RPW Maximum Ratings

Parameter
Symbol
Ratings
Unit
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ 3.6
V
Voltage on VDD supply relative to Vss
VDD
-1.0 ~ 3.6
V
Voltage on VDDQ supply relative to Vss
VDDQ
-0.5 ~ 3.6
V
Storage Temperature
TSTG
-55 ~ +150
°C
Power Dissipation
PD
18
W
Short Circuit Current
IOS
50
mA
Notes: Operation at above absolute maximum rating can adversely affect device reliability

HDD64M72D18RPW Features

• Part Identification
HDD64M72D18RPW 10A : 100MHz (CL=2)
HDD64M72D18RPW 13A : 133MHz (CL=2)
HDD64M72D18RPW 13B : 133MHz (CL=2.5)
• 512MB(64Mx72) Registered DDR DIMM based on 32Mx8 DDR SDRAM
• 2.5V ± 0.2V VDD and VDDQ power supply
• Auto & self refresh capability (8K Cycles / 64ms)
• All input and output are compatible with SSTL_2 interface
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• MRS cycle with address key programs
- Latency (Access from column address) : 2, 2.5
- Burst length : 2, 4, 8
- Data scramble : Sequential & Interleave
• Data(DQ), Data strobes and write masks latched on the rising and falling edges of the clock
• All Addresses and control inputs except Data(DQ), Data strobes and Data masks latched on the rising edges of the clock
• The used device is 8M x 8bit x 4Banks DDR SDRAM

HDD64M72D18RPW datasheet

HDD100
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