HEF40193B General Description
The HEF40193B is a 4-bit synchronous up/down binary counter. The counter has a count-up clock input (CPU), a count-down clock input (CPD), an asynchronous parallel load input (PL), four parallel data inputs (P0 to P3), an asynchronous master reset input (MR), four counter outputs (O0 to O3), an active LOW terminal count-up (carry) output (TCU) and an active LOW terminal count-down (borrow) output (TCD).
The counter outputs change state on the LOW to HIGH transition of either clock input. However, for correct counting, both clock inputs cannot be LOW simultaneously. The outputs TCU and TCD are normally HIGH. When the circuit has reached the maximum count state of '15', the next HIGH to LOW transition of CPU will cause TCU to go LOW. TCU will stay LOW until CPU goes HIGH again. Likewise, output TCD will go LOW when the circuit is in the zero state and CPD goes LOW. When PL is LOW, the information on P0 to P3 is asynchronously loaded into the counter. A HIGH on MR resets the counter independent of all other input conditions. The counter stages are of a static toggle type flip-flop.
HEF40193B Typical Application
Some examples of applications for the HEF40193B are:
· Up/down difference counting
· Multistage ripple counting
· Multistage synchronous counting
HEF40193B Connection Diagram
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