HEF4024B

Application

Some examples of applications for the HEF4024B are:
· Frequency dividers
· Time delay circuits


Pinout




Description

The HEF4024B is a 7-stage binary ripple counter with a clock input (CP), and overriding asynchronous master reset input (MR) and seven fully buffered parallel outputs (O0 to O6). The counter advances on the HIGH to LOW transition of CP. A HIGH on MR clears all HEF4024B counter stages and forces all outputs LOW, independent of CP. Each counter stage is a static toggle flip-flop.