HEF4510B

The HEF4510B is an edge-triggered synchronous up/down BCD counter with a clock input (CP), an up/down count control input (UP/DN), an active LOW count enable input (CE), an asynchronous active HIGH parallel load input (PL), four parallel inputs (P₀ to P₃), four parallel outputs (O₀ to O₃), an active LOW terminal count output (TC), and an overriding asynchronous master reset input (MR).

Information on P₀ to P₃ is loaded into the counter while PL is HIGH, independent of all other input conditions of HEF4510B except the MR input, which must be LOW. With PL LOW, the HEF4510B counter changes on the LOW to HIGH transition of CP if CE isLOW. UP/DN determines the direction of the count, HIGH for counting up, LOW for counting down. When counting up, TC is LOW when O₀ and O₃ are HIGH and CE is LOW. When counting down, TC is LOW when O0 to O3 and CE are LOW. A HIGH on MR resets the counter (O₀ to O₃ = LOW) independent of all other input conditions.