HEF4518B

T he HEF4518B is a dual 4-bit internally synchronous BCD counter. The counter has an active HIGH clock input (CP₀) and an active LOW clock input (CP₁), buffered outputs from all four bit positions (O0 to O3) and an active HIGH overriding asynchronous master reset input (MR).

The counter advances on either the LOW to HIGH transition of the CP0 input if CP₁ is HIGH or the HIGH to LOW transition of theCP₁ input if CP0 is LOW. Either CP₀ or CP1 may be used as the clock input to the counter and the other clock input may be used as a clock enable input. A HIGH on MR resets the counter (O₀ to O₃ = LOW) independent of CP₀, CP₁.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.