HEF4534BD_1099764

The HEF4534B is a 5-decade ripple counter. The binary utputs of the decade counters are time-multiplexed by an nternal scanner on four BCD outputs (O₀ to O₃). The elected decade is indicated by a logic HIGH on the ppropriate digit select output (OS₀: units, 1; OS₁: tens, 0; OS₂: hundreds, 10²;OS₃: thousands, 10³; OS₄: ten housands, 10⁴).

The binary outputs (O₀ to O₃) and the select outputs OS₀ to OS₄) of HEF4534B are 3-state controlled via enable inputs O and EOS respectively, allowing interface with other us orientated devices. Cascading may be accomplished y using the carry out (TC). The counter is triggered by a OW to HIGH transition on the decade clock (CPA) and is eset by a HIGH level on the master reset (MR). The scanner is triggered by a LOW to HIGH transition on the canner clock (CPS) and is reset (select ten thousand ounter) by a HIGH level on the scanner reset (MRsc). he counter can operate in four modes depending on the tate of the mode select inputs (S_A,S_B). The error detector ill detect an error when a positive edge on CPA is not ccompanied by a negative edge on the error detector lock CPE or vice versa, within time limits adjusted by xternal capacitors connected to C_{ext 1} and C_{ext 2}. Three or ore detected errors result in a HIGH level on the error utput (OER). The error detector is reset by a HIGH level n MR.

Schmitt-trigger action in the clock inputs makes the HEF4534B circuit ighly tolerant to slower clock rise and fall times.