HIP1011E

Features:

• Independent Power Control of 2 PCI Slots
• Turn-Off Delay Time Adjustability
• Internal MOSFET Switches for +12V and -12V Outputs
• P Interface for On/Off Control and Fault Reporting
• Adjustable Overcurrent Protection for All Eight Supplies
• Provides Fault Isolation
• Adjustable Turn-On Slew Rate
• Minimum Parts Count Solution
• No Charge Pump
• 100ns Response Time to Overcurrent
• Pb-Free Available (RoHS Compliant)




Application

• PCI Hot-Plug




Pinout






Specifications

12VIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +14.0V
12VO, 12VG, 3V5VG . . . . . . . . . . . . . . . . . -0.5V to 12VIN+0.5V
M12VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -14.0V to +0.5V
M12VO, M12VG. . . . . . . . . . . . . . . . . . . V_M12VIN-0.5V to +0.5V
3VISEN, 5VISEN . . . . . . -0.5V to the Lesser of 12VIN or +7.0V
Voltage, Any Other Pin. . . . . . . . . . . . . . . . . . .. -0.5V to +7.0V
12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3A
M12VO Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8A
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . .2KeV (HBM)




Description

The HIP1011D, HIP1011E are the first ICs available for independent control of two PCI Hot-Plug slots. The HIP1011D has all the features and functionality of two single PCI Hot-Plug slot controllers such as the HIP1011A but in the same foot print area. Like the single slot HIP1011B, the HIP1011E does not monitor output voltage nor respond to undervoltage conditions. The HIP1011D, HIP1011E are designed to be physically placed in close proximity to two adjacent PCI slots thus reducing layout complexity and placement costs in assembly. The HIP1011D, HIP1011E provides independent power control to each slot and the addition of discrete power MOSFETs and a few passive components creates two complete power control solutions. The IC integrates the +12V and -12V current sensing switches for each slot. Overcurrent (OC) protection is provided by sensing the voltage across external current-sense resistors. In addition, on-chip references are used to monitor the +5V, +3.3V and +12V outputs for undervoltage (UV) conditions *. The two PWRON inputs control the state of the switches, one each for slot A and slot B outputs. During an OC condition on any output, or a UV condition on the +5V, +3.3V or +12V outputs *, a LOW (0V) is asserted on the associated FLTN output and all associated switches are latched-off. The outputs servicing the adjacent slot are unaffected. The time to FLTN signal going LOW and MOSFET latch off is user determined by a single capacitor from each FLTN pin to ground. This added feature enables the HIP1011D, HIP1011E to ignore system noise transients. The FLTN latch is cleared when the PWRON input is toggled low again. During initial power-up of the main VCC supply (+12V), the PWRON input is inhibited from turning on the switches, and the latch is held in the Reset state until the VCC input is greater than 10V. User programmability of the overcurrent threshold and turnon slew rate is provided. A resistor connected to the OCSET pin programs the overcurrent threshold for both slots. Capacitors connected to the gate pins set the turn-on rate.