HIP6604B

Designed for versatility and speed, the HIP6601B, HIP6603B and HIP6604B dual MOSFET drivers control both high-side and low-side N-Channel FETs from one externally provided PWM signal.


The upper and lower gates are held low until the driver is initialized. Once the VCC voltage surpasses the VCC Rising Threshold (See Electrical Specifications), the PWM signal takes control of gate transitions. A rising edge on PWM sinitiates the turn-off of the lower MOSFET (see Timing Diagram). After a short propagation delay [t_PDLLGATE ], the lower gate begins to fall. Typical fall times [t_FLGATE ] are provided in the Electrical Specifications section. Adaptive shoot-through circuitry monitors the LGATE voltage and determines the upper gate delay time [t_PDHUGATE ] based
on how quickly the LGATE voltage drops below 2.2V. This prevents both the lower and upper MOSFETs from conducting simultaneously or shoot-through. Once this delay period is complete the upper gate drive begins to rise [t _RUGATE] and the upper MOSFET turns on.


A falling transition on PWM indicates the turn-off of the upper MOSFET and the turn-on of the lower MOSFET. A short propagation delay [t_PDLUGATE ] is encountered before the upper gate begins to fall [t _FUGATE]. Again, the adaptive shoot-through circuitry determines the lower gate delay time, t_PDHLGATE . The PHASE voltage is monitored and the lower gate is allowed to rise after PHASE drops below 0.5V. The lower gate then rises [t_RLGATE], turning on the lower MOSFET.