HM-65162

Features:

• Fast Access Time  . . . . . . . . . . . . . . . . . . .  70/90ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . .50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
• Data Retention at 2.0V. . . . . . . . . . . .. . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout (2716, 6116 Type)
• No Clocks or Strobes Required
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs
• No Pull-Up or Pull-Down Resistors Required


Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . .  GND -0.3V to VCC +0.3V
Typical Derating Factor  . . . . . .. . . . . . 05mA/MHz Increase in ICCOP
ESD Classification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  Class 1


Description

The HM-65162 is a CMOS 2048 x 8 Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle time and ease of use. The pinout is the JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which allows easy memory board layouts flexible to accommodate a variety of industry standard PROMs, RAMs, ROMs and EPROMs. The HM-65162 is ideally suited for use in microprocessor based systems with its 8-bit word length organization. The conve-nient output enable also simplifies the bus interface by allow-ing the data outputs to be controlled independent of the chip enable. Gated inputs lower operating current and also elimi-nate the need for pull-up or pull-down resistors.