HM-65262

Features:

• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 70/85ns Max
• Low Standby Current. . . . . . . .  . . . . . . . . . . . . .50µA Max
• Low Operating Current  . . . . . . . .  . . . . . . . . . . 50mA Max
• Data Retention at 2.0V. . . . . . . . . . . . .  . . . . . . .20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout
• No Clocks or Strobes Required
• Temperature Range . . . . . . . . . . . . . . . . +55oC to +125oC
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs-No Pull-Up or Pull-Down Resistors
Required


Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V
Input or Output Voltage Applied for all grades  . . . . . -0.3V to VCC +0.3V
Typical Derating Factor . . . . . . . . . . . . . . . .5mA/MHz Increase in ICCOP
ESD Classification  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The HM-65262 is a CMOS 16384 x 1-bit Static Random Access Memory manufactured using the Intersil Advanced SAJI V process. The device utilizes asynchronous circuit design for fast cycle times and ease of use. The HM-65262 is available in both JEDEC standard 20 pin, 0.300 inch wide CERDIP and 20 pad CLCC packages, providing high board-level packing density. Gated inputs lower standby current,and also eliminate the need for pull-up or pull-down resis-tors.

The HM-65262, a full CMOS RAM, utilizes an array of six transistor (6T) memory cells for the most stable and lowest possible standby supply current over the full military temper-ature range. In addition to this, the high stability of the 6T RAM cell provides excellent protection against soft errors due to noise and alpha particles. This stability also improves the radiation tolerance of the RAM over that of four transistor (4T) devices.