HM-6642

Features:

• Low Power Standby and Operating Power
        - ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100mA
        - ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable


Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to V_CC +0.3V
Typical Derating Factor . . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1


Description

The HM-6642 is a 512 x 8 CMOS NiCr fusible link Programmable Read Only Memory in the popular 24 pin, byte wide pinout. Synchronous circuit design techniques combine with CMOS processing to give this HM-6642 device high speed performance with very low power dissipation.

On-chip address latches are provided, allowing easy interfacing with recent generation microprocessors that use multiplexed address/data bus structures, such as the 8085.The output enable controls, both active low and active high, further simplify microprocessor system interfacing by allowing output data bus control independent of the chip enable control. The data output latches allow the use of the HM-6642 in high speed pipelined architecture systems, and also in synchronous logic replacement functions.

Applications for the HM-6642 CMOS PROM include low power handheld microprocessor based instrumentation and communications systems, remote data acquisition and processing systems, processor control store, and synchronous logic replacement.
All bits are manufactured storing a logical "0" and can be selectively programmed for a logical "1" at any bit location.