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Part Number: HM64YLB36514
Description: The HM64YLB36514 is a synchronous fast static RAM organized as 512-kword × 36-bit. It has realized hig...
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HM64YLB36514
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DataSheet
General Description
HM64YLB36514 General Description
The HM64YLB36514 is a synchronous fast static RAM organized as 512-kword × 36-bit. It has realized high speed access time by employing the most advanced CMOS process and high speed circuit designing technology. It is most appropriate for the application which requires high speed, high density memory and wide bit width configuration, such as cache and buffer memory in system. It is packaged in standard 119- bump BGA.
Note: All power supply and ground pins must be connected for proper operation of the device.
HM64YLB36514 Maximum Ratings
| Parameter |
Symbol |
Rating |
Unit |
Notes |
| Input voltage on any pin |
VIN |
−0.5 to VDDQ + 0.5 |
V |
1, 4 |
| Core supply voltage |
VDD |
−0.5 to +3.13 |
V |
1 |
| Output supply voltage |
VDDQ |
−0.5 to +2.1 |
V |
1, 4 |
| Operating temperature |
TOPR |
0 to +85 |
||
| Storage temperature |
TSTG |
−55 to +125 |
||
| Output short-circuit current |
IOUT |
25 |
mA |
|
| Latch up current |
ILI |
200 |
mA |
|
| Package junction to top thermal resistance |
J-top |
6.5 |
/W |
5 |
| Package junction to board thermal resistance |
J-board |
12 |
/W |
5 |
HM64YLB36514 Features
• 2.5 V ± 5% operation and 1.5 V (VDDQ)
• 16M bit density
• Internal self-timed late write
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• Programmable impedance output drivers
• Differential pseudo-HSTL clock inputs
• Asynchronous G output control
• Asynchronous sleep mode
• FC-BGA 119pin package with SRAM JEDEC standard pinout
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Protocol: Single differential clock register-latch mode
• 16M bit density
• Internal self-timed late write
• Byte write control (4 byte write selects, one for each 9-bit)
• Optional ×18 configuration
• HSTL compatible I/O
• Programmable impedance output drivers
• Differential pseudo-HSTL clock inputs
• Asynchronous G output control
• Asynchronous sleep mode
• FC-BGA 119pin package with SRAM JEDEC standard pinout
• Limited set of boundary scan JTAG IEEE 1149.1 compatible
• Protocol: Single differential clock register-latch mode
HM6116
PDF/DataSheet Download
- Datasheet: HM6116
- File Size: 256425 KB
- Manufacturer: HITACHI [Hitachi Semiconductor]
- Click here to Download
- ·HM6116FP-2
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
- ·HM6116FP-3
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
- ·HM6116FP-4
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
- ·HM6116LFP-2
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
- ·HM6116LFP-3
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
- ·HM6116LFP-4
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
- ·HM6116LP-2
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
- ·HM6116LP-3
- HITACHI [Hitachi Semiconductor]
- 2048-word X 8bit High Speed CMOS Static RAM
- 256425 KB
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