HMA883

Features:

• This Circuit is Processed in Accordance to MIL-STD- 883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.
• 16 x 16-Bit Parallel Multiplication with Accumulation to a 35-Bit Result
• High-Speed (55ns) Multiply Accumulate Time
• Low Power CMOS Operation
     - I_CCSB = 500mA Maximum
     - I_CCOP = 7.0mA Maximum at 1.0MHz
• HMA510/883 is Compatible with the CY7C510 and the IDT7210
• Supports Two's Complement or Unsigned Magnitude Operations
• Three-State Outputs


Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . .+8.0V
Input or Output Voltage Applied . . . . . . . . G ND -0.5V to V_CC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .  Class 1


Description

The HMA510/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier accumulator capable of operating at 55ns clocked multiply-accumulate cycles. The 16-bit X and Y operands may be specified as either two's complement or unsigned magnitude format. Additional inputs are provided for the accumulator functions which include: loading the accumulator with the current product, adding or subtracting the accumulator contents and the current product, and preloading the Accumulator Registers from the external inputs.

All inputs and outputs of HMA510/883 are registered. The HMA510/883 registers are all positive edge triggered, and are latched on the rising edge of the associated clock signal. The 35-bit Accumulator Output Register is broken into three parts. The 16-bit least signifi- cant product (LSP), the 16-bit most significant product (MSP), and the 3-bit extended product (XTP) Registers. The XTP and MSP Registers have dedicated output ports, while the LSP Register shares the Y-inputs in a multiplexed fashion. The entire 35-bit Accumulator Output Register may be preloaded at any time through the use of the bidirectional output ports and the preloaded control.