Features: · HVCMOS® technology· Operating output voltage of 300V· Low power level shifting from 5V to 300V· Shift register speed 8MHz @ VDD = 5V· 64 latched data outputs· Output polarity and blanking· CMOS compatible inputs· Forward and reverse shifting optionsPinoutSpecificationsSupply voltag...
HV507: Features: · HVCMOS® technology· Operating output voltage of 300V· Low power level shifting from 5V to 300V· Shift register speed 8MHz @ VDD = 5V· 64 latched data outputs· Output polarity and bla...
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The HV507 is a low voltage serial to high voltage parallel converter with 64 high voltage push-pull outputs. This device has been designed for use as a printer driver for electrostatic applications. It can also be used in any application requiring multiple high voltage outputs, low current sourcing and sinking capabilities.
The device HV507 consists of a 64-bit shift register, 64 latches, and control logic to perform the polarity select and blanking of the outputs. A DIR pin controls the direction of data shift through the device. With DIR grounded, DIOA is Data In and DIOB is Data Out; data is shifted from HVOUT64 to HVOUT1. When DIR is at logic high, DIOB is Data In and DIOA is Data Out: data is then shifted from HVOUT1 to HVOUT64. Data is shifted through the shift register on the low to high transition of the clock. Data output buffers are provided for cascading devices. Operation of the shift register is not affected by the LE, BL, or the POL inputs. Transfer of data from the shift register to the latch occurs when the LE is high. The data in the latch is stored during LE transition from high to low,that is the info about HV507.