HV509

Features: ·HVCMOS® technology·Output voltage up to +200V·Shift register speed 500kHz @ VDD = 2.0V·16 high voltage outputs·High voltage backplane driver·CMOS input levelsApplication·Multiple segment EL display·Piezoelectric transducer driver·Braille driverPinoutSpecifications Parameter ...

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HV509 Picture
SeekIC No. : 004367548 Detail

HV509: Features: ·HVCMOS® technology·Output voltage up to +200V·Shift register speed 500kHz @ VDD = 2.0V·16 high voltage outputs·High voltage backplane driver·CMOS input levelsApplication·Multiple segm...

floor Price/Ceiling Price

Part Number:
HV509
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/28

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Product Details

Description



Features:

·HVCMOS® technology
·Output voltage up to +200V
·Shift register speed 500kHz @ VDD = 2.0V
·16 high voltage outputs
·High voltage backplane driver
·CMOS input levels



Application

·Multiple segment EL display
·Piezoelectric transducer driver
·Braille driver



Pinout

  Connection Diagram


Specifications

Parameter
Value
Logic supply, VDD
-0.5V to 7.0V
High voltage supply, VPP
215V
Translator supply voltage, VBIAS
-0.5V to 7.0V
Logic input levels
-0.5V to VDD + 0.5V
Operating junction temperature
-40°C to +125°C
Storage temperature range
-65°C to +150°C

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.




Description

The HV509 is a 200V, 16-channel serial to parallel converter. The high voltage outputs and the backplane driver are design d to source and sink ±1.0mA.

The high voltage outputs of HV509 are controlled by a 16-bit serial shift register, followed by a 16-bit latch. Data is shifted through the shift registers during the low to high clock transition. A data output buffer is provided for cascading multiple devices. Data is transferred to the 16-bit latch when a logic level low is applied to the LE input. Data is stored in the latch when LE is high. Output states are controlled by the data in the latch and by the POL pin.




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