HV6506

Features: · Processed with HVCMOS® technology· 32 push-pull CMOS output up to 60V· Low power level shifting· Source/sink current minimum 5mA· Shift register speed 5MHz· Latched data outputs· Bidirectional shift register (DIR)· Backplane outputSpecificationsSupply voltage, VDD........ 2 -0.5V t...

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SeekIC No. : 004367580 Detail

HV6506: Features: · Processed with HVCMOS® technology· 32 push-pull CMOS output up to 60V· Low power level shifting· Source/sink current minimum 5mA· Shift register speed 5MHz· Latched data outputs· Bid...

floor Price/Ceiling Price

Part Number:
HV6506
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/4/27

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Product Details

Description



Features:

· Processed with HVCMOS® technology
· 32 push-pull CMOS output up to 60V
· Low power level shifting
· Source/sink current minimum 5mA
· Shift register speed 5MHz
· Latched data outputs
· Bidirectional shift register (DIR)
· Backplane output



Specifications

Supply voltage, VDD........ 2 -0.5V to +7.0V
Output voltage, VPP
..................  2 -0.5V to +80V
Logic input levels2 ......  -0.5V to VDD + 0.5V
Ground current3 ..............1.5A
Continuous total power dissipation4... 1200mW
Operating temperature range..      -40 to +85
Storage temperature range ...   -65 to +125
Lead temperature 1.6mm (1/16 inch)....  260
from case for 10 seconds



Description

The HV6506 is a low-voltage serial to high-voltage parallel converter with push-pull outputs. This device has been designed for use as a driver circuit for LCD displays. It can also be used in any application requiring multiple output high-voltage current sourcing and sinking capabilities. The inputs are fully CMOS compatible.

The device HV6506 consists of a 32-bit shift register, 32 latches, and control logic to perform the polarity select of the outputs. HVout1 is connected to the first stage of the shift register through the polarity logic. Data is shifted through the shift register on the logic low to high transition of the clock. A DIR pin causes data shifting counterclockwise when grounded and clockwise when connected to VDD. A data output buffer is provided for cascading devices.

HV6506 output reflects the current status of the last bit of the shift register. Operation of the shift register is not affected by the LE (latch enable) or the POL (polarity) inputs. Transfer of data from the shift register to the latch occurs when the LE (latch enable) input is high. The data in the latch is stored after LE transition from high to low.




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