Purchase HY5PS1G421M, In-stock HY5PS1G421M From SeekIC.
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HY5PS1G421M
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DataSheet
General Description
HY5PS1G421M General Description
HY5PS1G421M Maximum Ratings
| Symbol | Parameter | Rating | Units | Note |
| VDD | Voltage on VDD pin relative to VSS | - 1.0 V ~ 2.3 V | V | 1 |
| VDDQ | Voltage on VDDQ pin relative to VSS | - 0.5 V ~ 2.3 V | V | 1 |
| VDDL | Voltage on VDDL pin relative to VSS | - 0.5 V ~ 2.3 V | V | 1 |
| VIN, VOUT | Voltage on any pin relative to VSS | - 0.5 V ~ 2.3 V | V | 1 |
| TSTG | Storage Temperature | -55 to +100 | 1 |
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the evice. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating onditions for extended periods may affect reliability.
HY5PS1G421M Features
• Dual Die Package( 512Mb DDR2 * 2)
• VDD, VDDQ=1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 3, 4, 5 supported
• Programmable additive latency 0, 1, 2, 3, 4 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal 4bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
• VDD, VDDQ=1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
• Programmable CAS latency 3, 4, 5 supported
• Programmable additive latency 0, 1, 2, 3, 4 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal 4bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
HY50P
PDF/DataSheet Download
- Datasheet: HY50P
- File Size: 121146 KB
- Manufacturer: LEM [LEM]
- Click here to Download
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