Purchase HY5PS1G431CFP, In-stock HY5PS1G431CFP From SeekIC.
- Table of contents:
HY5PS1G431CFP
-
Suppliers
DataSheet
General Description
HY5PS1G431CFP Maximum Ratings
| Symbol | Parameter | Rating | Units | Notes |
| VDD | Voltage on VDD pin relative to Vss | - 1.0 V ~ 2.3 V | V | 1 |
| VDDQ | Voltage on VDDQ pin relative to Vss | - 0.5 V ~ 2.3 V | V | 1 |
| VDDL | Voltage on VDDL pin relative to Vss | - 0.5 V ~ 2.3 V | V | 1 |
| VIN, VOUT | Voltage on any pin relative to Vss | - 0.5 V ~ 2.3 V | V | 1 |
| II | Input leakage current; any input 0V VIN VDD; all other balls not under test = 0V) |
-2 uA ~ 2 uA | uA | |
| IOZ | Output leakage current; 0V VOUT VDDQ; DQ and ODT disabled |
-5 uA ~ 5 uA | uA | |
| TSTG | Storage Temperature | -55 to +100 | 1,2 |
Note:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the /top side of the DRAM. For the measurement conditions. please refer to JESD51-2 standard.
HY5PS1G431CFP Features
• VDD = 1.8V +/- 0.1V
• VDDQ = 1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• 8 banks
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal eight bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) , 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
• VDDQ = 1.8V +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• 8 banks
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4/8 with both nibble sequential and interleave mode
• Internal eight bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) , 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
HY50P
PDF/DataSheet Download
- Datasheet: HY50P
- File Size: 121146 KB
- Manufacturer: LEM [LEM]
- Click here to Download
- ·HY50-P
- LEM [LEM]
- Current Transducer HY 50-P
- 133163 KB
- ·HY5116404B
- Hyundai
- 104611 KB
- ·HY5117404B
- Hyundai
- 104611 KB
- ·HY5117404BJ-60
- x4 EDO Page Mode DRAM
- 438835 KB
- ·HY5118164
- Hynix
- IC,DRAM,EDO,1MX16,CMOS,SOJ,42PIN,PLASTIC
- 471769 KB
- ·HY514400
- ETC [ETC]
- 1M x 4-bit CMOS DRAM
- 938750 KB
- ·HY514400A
- ETC [ETC]
- 1M x 4-bit CMOS DRAM
- 823647 KB
- ·HY514400AJ
- ETC [ETC]
- 1M x 4-bit CMOS DRAM
- 823647 KB
HY5PS1G431CFP Relative Products
HY5PS1G431(L)F
HY5PS1G421M
HY5PS12821L
HY5PS12821FP
The features of HY5PS12821FP: 1.1 Device Features and Ordering Information1.1.1 Key Feaures1.1.2 Ordering Information1.1.3 Ordering Frequency1.2 Pin configuration1.3 Pin Description
HY5PS12821F
HY5PS12421L
Hotspot Suppliers Product
MPF102
Price: 0.12-0.15 USD
MPF102. TO-92. G. S D. N-Channel RF Amplifier
TEESVA0J476M8R
Price: 0.1-100 USD
6.3 V,SMD, Tantalum Capacitor, RoHS Compliant, high-capacity model, NEC, TEESVA0J476M8R
AD608ARZ
Price: 0.5-0.65 USD
low Power Mixer/Limiter, 3V, 16-SOIC
XC2VP20-5FG676I
Price: 110-215 USD
Platform Flash In-System, Programmable Configuration PROMS, BGA, 1.5V to 3.3V
L5973AD
Price: 0.5-0.8 USD
3.3V, 2A, 500KHz, power switching regulator, 40 V, Low dropout operation
TVP7002PZP
Price: 2-5 USD
complete solution, 100-HTQFP, –0.5 V to 4.5 V, 12-MHz to 165-MHz, Automatic Video Clamp
NRF905
Price: 2.8-4 USD
single chip system, RF transceiver, 8051 compatible microcontroller
HE1AN-DC24V
Price: 0.1-100 USD
HE relay, 30A, 24VDC, 1.92 W, 300 Ohms, Excellent resistance, High-capacity, Excellent surge res...
EP9301-IQZ
Price: 18.8-18.85 USD
MCU, 208-LQFP, 166 MHz, ARM9 processor, 3.96V, 2W, ±10mA, 16-kbyte Instruction Cache
MAX3232
Price: 0.1-1 USD
transceiver, 3.0V to 5.5V, SOP
XC17V04VQ44C
Price: 50-55 USD
configuration PROM, 4MBIT, 3.3V, 44-VQFP, XC17V04VQ44C, Xilinx
RC28F128J3C150
Price: 1-7 USD
StrataFlash memory, BGA, 100 mA
