HYB18T256324F22

    The Infineon 256-Mbit GDDR3 DRAM [600MHz]is a high speed memory device, designed for high bandwidth intensive applications like PC graphics systems. The chip's quad bank architecture is optimized for high speed and achieves a peak bandwidth of 8 Gbyte/s using a 32 bit interface and a maximum system clock of 600 MHz.

    HYB18T256324F[16/20/22] uses a double data rate interface and a 4n-prefetch architecture. The GDDR3 interface transfers two 32 bit wide data words per clock cycle to/from the I/O pins. Corresponding to the 4n prefetch a single write or read access consists of a 128 bit wide, one-clock-cycle data transfer at the internal memory core and four corresponding 32 bit wide, one-half-clock-cycle data transfers at the I/O pins.

    Single-ended unidirectional Read and Write Data strobes are transmitted simultaneously with Read and Write data respectively in order to capture data properly at the receivers of both the Graphics SDRAM and the controller. Data strobes are organized per byte of the 32 bit wide interface. For read commands the RDQS are edge-aligned with data, and the WDQS are center aligned with data for write commands.

    The HYB18T256324F[16/20/22] operates from a differential clock (CLK and CLK). Commands (addresses and control signals) are registered at every positive edge of CLK. Input data is registered on both edges of WDQS, and output data is referenced to both edges of RDQS.

    In this document references to 'the positive edge of CLK' imply the crossing of the positive edge of CLK and the negative edge of CLK. Similarly, the 'negative edge of CLK' refers to the crossing of the negative edge of CLK and the positive edge of CLK. References to RDQS are to be interpreted as any or all RDQS<3:0>. WDQS, DM and DQ should be interpreted in a similar fashion.

    Read and write accesses to the HYB18T256324F [16/20/22] are burst oriented. The burst length is fixed to 4 and the two least significant bits of the burst address are 'Don't Care' and internally set to LOW. Accesses begin with the registration of an ACTIVATE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVATE command are used to select the bank and the row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the column location for the burst access. Each of the 4 banks consists of 4096 row locations and 512 column locations. An AUTO PRECHARGE function can be combined with READ and WRITE to provide a self timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of the HYB18T256324F[16/20/22] allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.

    The device is supplied with 2.0 V for output drivers and core. (V_DD / V_DDQ voltages see Table 1).

    The "On Die Termination" interface (ODT) is optimized for high frequency digital data transfers and is internally controlled. The termination resistor value can be set using an external ZQ resistor or disabled through the Extended Mode Register.

    The output driver impedance can be set using the Extended Mode Register. It can either be set to ZQ / 6 (autocalibration) or to 35, 40 or 45 Ohms.

    Auto Refresh and Power Down with Self Refresh operations are supported. 

    A standard  P-TBGA 144 package is used which enables ultra high speed data transfer rates and a simple upgrade path from former DDR Graphics SDRAM products.