HYB18T256400AF

  The 256Mb Double-Data-Rate-2 (DDR2) DRAMs are highspeed CMOS Double Data Rate 2 Synchronous DRAM devices containing 268,435,456 bits and are internally configured as a quad-bank DRAMs. The 256Mb chip is organized as either 16Mbit x 4 I/O x 4 bank, 8Mbit x 8 I/O x 4 bank or 4Mbit x 16 I/O x 4 bank device. These synchronous devices achieve high speed double-data-rate transfer rates of up to 667 Mb/sec/pin for general applications.
  The chip is designed to comply with all key DDR2 DRAM key features: (1) posted CAS with additive latency, (2) write
latency = read latency -1, (3) normal and weak strength dataoutput driver, (4) Off-Chip Driver (OCD) impedance adjustment and (5) an ODT (On-Die Termination) function.
  All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single
ended DQS or differential (DQS, DQS) pair in a source synchronous fashion. A 15 bit address bus is used to convey
row, column and bank address information in a RAS / CAS multiplexing style.
  The DDR2 devices operate with a 1.8V +/-0.1V power supply and are available in FBGA packages.

  An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.
  The functionality described and the timing specifications
included in this data sheet are for the DLL Enabled mode
of operation.