Features: The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O• DRAM organizations with 4, 8 and 16 data in/outputs• Double Data Rate architecture: two data transfers per clock cycle four int...
HYB18T256400BF-25F: Features: The 256-Mbit Double-Data-Rate-Two SDRAM offers the following key features:• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O• DRAM organizations with 4, 8 and ...
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Symbol |
Parameter |
Rating |
Unit |
Note | |
Min. |
Max. | ||||
VDD |
Voltage on VDD pin relative to VSS |
1.0 |
+2.3 |
V |
1) |
VDDQ |
Voltage on VDDQ pin relative to VSS |
0.5 |
+2.3 |
V |
1)2) |
VDDL |
Voltage on VDDL pin relative to VSS |
0.5 |
+2.3 |
V |
1)2) |
VIN, VOUT |
Voltage on any pin relative to VSS |
0.5 |
+2.3 |
V |
1) |
TSTG |
Storage Temperature |
55 |
+100 |
1)2) |
The 256-Mbit Double-Data-Rate-Two SDRAM HYB18T256400BF-25F is a highspeed CMOS Synchronous DRAM device containing 268,435,456 bits and internally configured as a quad-bank DRAM. The device is organized as either 16 Mbit × 4 I/O × 4 banks, 8 Mbit × 8 I/O × 4 banks or 4 Mbit ×16 I/O × 4 banks chip. These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 for performance figures.
The device HYB18T256400BF-25F is designed to comply with all DDR2 DRAM key features:
• Posted CAS with additive latency,
• Write latency = read latency - 1,
• Normal and weak strength data-output driver,
• Off-Chip Driver (OCD) impedance adjustment
• On-Die Termination (ODT) function.
All of the HYB18T256400BF-25F control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.
A is used to convey row, column and bank address information in a RAS-CAS multiplexing style.
The DDR2 device HYB18T256400BF-25F operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.
The HYB18T256400BF-25F functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of
operation.
The DDR2 SDRAM HYB18T256400BF-25F is available in P(G)-TFBGA-60 and P(G)- TFBGA-84 packages.