HYB18T512400AF

The 512-Mb DDR2 DRAM is a high-speed Double-Data-Rate-2 CMOS Synchronous DRAM device containing 536,870,912 bits and internally configured as a quad-bank DRAM. The 512-Mb device is organized as either 32 Mbit × 4 I/O × 4 banks, 16 Mbit × 8 I/O × 4 banks or 8 Mbit × 16 I/O × 4 banks chip.These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 3 for performance figures.

The device is designed to comply with all DDR2 DRAM key features:
1. posted CAS with additive latency,
2. write latency = read latency - 1,
3. normal and weak strength data-output driver,
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function.

All of the control and address inputs are synchronized with a pair of externally supplied differential clocks.Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended DQS or differential DQS-DQS pair in a source synchronous fashion.A 16-bit address bus for ×4 and ×8 organised components and a 15-bit address bus for ×16 components is used to convey row, column and bank address information in a RAS-CAS multiplexing style.

The DDR2 device operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes.

The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation. The DDR2 SDRAM is available in P-TFBGA package.