HYB18TC1G800AF

• 1.8 V ± 0.1 V Power Supply 1.8 V ± 0.1 V (SSTL_18) compatible I/O
• DRAM organizations with 8, 16 data in/outputs
• Double Data Rate architecture: two data transfers per clock cycle four internal banks for concurrent operation
• CAS Latency: 3, 4, 5
• Burst Length: 4 and 8
• Differential clock inputs (CK and CK)
• Bi-directional, differential data strobes (DQS and DQS) are transmitted / received with data. Edge aligned with read data and center-aligned with write data.
• DLL aligns DQ and DQS transitions with clock
• DQS can be disabled for single-ended data strobe operation
• Commands entered on each positive clock edge, data and data mask are referenced to both edges of DQS
• Data masks (DM) for write data
• Posted CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality.
• Auto-Precharge operation for read and write bursts
• Auto-Refresh, Self-Refresh and power saving Power-Down modes
• Average Refresh Period 7.8 s at a TCASE lower than 85 °C, 3.9 s between 85 °C and 95 °C
• Programmable self refresh rate via EMRS2 setting
• DCC enabling via EMRS2 setting
• Full and reduced Strength Data-Output Drivers
• 1K page size for *8, 2K page size for *16
• Packages: PG-TFBGA-68 for *8 components PG-TFBGA-92 for *16 components
• RoHS Compliant Products1)
• All Speed grades faster than DDR400 comply with DDR2400 timing specifications when run at a clock rate of 200 MHz.
A list of the performance tables for the various speeds can be found below

The 1-Gb DDR2 DRAM HYB18TC1G800AF is a high-speed Double-Data-Rate- Two CMOS Synchronous DRAM device containing 1,073,741,824 bits and internally configured as anoctal quadbank DRAM. The 1-Gb device is organized as either 16 Mbit ×8 I/O ×8 banks or 8 Mbit ×16 I/O ×8 banks chip. These synchronous devices achieve high speed transfer rates starting at 400 Mb/sec/pin for general applications. See Table 1 to Table 3 for performance figures.The device is designed to comply with all DDR2 DRAM key features:
1. Posted CAS with additive latency
2. Write latency = read latency - 1
3. Normal and weak strength data-output driver
4. Off-Chip Driver (OCD) impedance adjustment
5. On-Die Termination (ODT) function

All of the HYB18TC1G800AF control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK falling). All I/Os are synchronized with a single ended
DQS or differential DQS-DQS pair in a source synchronous fashion.

A 17 bit address bus for ×4 and ×8 organised components and a 16 bit address bus for ×16 components is used to convey row, column and bank address information in a RAS-CAS multiplexing style.

The DDR2 device HYB18TC1G800AF operates with a 1.8 V ± 0.1 V power supply. An Auto-Refresh and Self-Refresh mode is provided along with various power-saving power-down modes. The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.The DDR2 SDRAM is available in PG-TFBGA package.