HYB3117405BJ/BT(L)-70

Features:

• Single + 3.3 V (± 0.3V ) supply
• Low power dissipation
max. 396 active mW (HYB3117405BJ/BT-50)
max. 363 active mW (HYB3117405BJ/BT-60)
max. 330 active mW (HYB3117405BJ/BT-70)
max. 360 active mW (HYB3116405BJ/BT-50)
max. 324 active mW (HYB3116405BJ/BT-60)
max. 288 active mW (HYB3116405BJ/BT-70)
7.2 mW standby (LV-TTL)
3.6 mW standby (LV-CMOS)
720 mW standby for L-version
• Output unlatched at cycle end allows two-dimensional chip selection
• Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,Self   Refresh and test  mode
• Hyper page mode (EDO) capability
• All inputs, outputs and clocks fully TTL-compatible
• 2048 refresh cycles / 32 ms for HYB3117405
4096 refresh cycles / 64 ms for HYB3116405
• Plastic Package: P-SOJ-26/24-1 (300 mil)
                             P-TSOPII-26/24-1 (300mil)


Description

The HYB3117405BJ/BT(L)-70 is a 16MBit dynamic RAM organized as 4194304 words by 4-bits. The HYB 3116(7)405BJ/BT(L) utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 3116(7)405BJ/BT(L) to be packaged in a standard SOJ 26/24 300 mil or TSOPII-26/24 300 mil wide plastic package. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. System-oriented features include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families.The HYB3117405BJ/BT(L)-70 parts have a very low power „sleep mode" supported by Self Refresh.