HYB39S16800BT

Features: • Fully Synchronous to Positive Clock Edge• 0 to 70 °C operating temperature• Dual Banks controlled by A11 ( Bank Select)• ProgrammableCAS Latency : 2, 3• Programmable Wrap Sequence : Sequential or Interleave• Programmable Burst Length: 1, 2, 4, 8̶...

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SeekIC No. : 004368988 Detail

HYB39S16800BT: Features: • Fully Synchronous to Positive Clock Edge• 0 to 70 °C operating temperature• Dual Banks controlled by A11 ( Bank Select)• ProgrammableCAS Latency : 2, 3• Pro...

floor Price/Ceiling Price

Part Number:
HYB39S16800BT
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/28

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Product Details

Description



Features:

• Fully Synchronous to Positive Clock Edge
• 0 to 70 °C operating temperature
• Dual Banks controlled by A11 ( Bank Select)
• Programmable CAS Latency : 2, 3
• Programmable Wrap Sequence : Sequential or Interleave
• Programmable Burst Length: 1, 2, 4, 8
• full page(optional) for sequencial wrap around
• Multiple Burst Read with Single Write Operation
• Automatic and Controlled Precharge Command
• Data Mask for Read / Write control (x4, x8)
• Dual Data Mask for byte control ( x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• 4096 refresh cycles / 64 ms
• Random Column Address every CLK ( 1-N Rule)
• Single 3.3V +/- 0.3V Power Supply
• LVTTL Interface
• Plastic Packages:
   P-TSOPI-44 400mil width ( x4, x8 )
   P-TSOPII -50 400 mil width ( x 16 )
• -8 version for PC100 applications
 


Pinout

  Connection Diagram




Specifications

Operating temperature range ................................. 0 to + 70 °C
Storage temperature range................................ 55 to + 150 °C
Input/output voltage ........................ 0.5 to min(Vcc+0.5, 4.6) V
Power supply voltage VDD / VDDQ........................ 1.0 to + 4.6 V
Power Dissipation............................................. ............ ..........1 W
Data out current (short circuit) ............................................ 50 mA

Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage of the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.



Description

The HYB39S16800BTare dual bank Synchronous DRAM' s based on the die revisions "D", & "E" and organized as 2 banks x 2MBit x4, 2 banks x 1MBit x8 and 2 banks x 512kbit x16 respectively. These synchronous devices achieve high speed data transfer rates up to 125 MHz byemploying a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with SIEMENS' advanced 16MBit DRAM process technology.

The device HYB39S16800BT is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock.

Operating the two memory banks in an interleaved fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 125 MHz is possible depending on burst length, CAS latency and speed grade of the device HYB39S16800BT.

Auto Refresh (CBR) and Self Refresh operation are supported. These devices HYB39S16800BT operate with a single 3.3V +/- 0.3V power supply and are available in TSOPII packages.

These Synchronous DRAM devices HYB39S16800BT are available with LV-TTL interfaces.




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