HYE18M512160BF-7.5

Features: • 4 banks * 8 Mbit * 16 organization• Double-data-rate architecture : two data transfers per clock cycle• Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver• DQS is edge-aligned with data for READs and...

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HYE18M512160BF-7.5 Picture
SeekIC No. : 004369067 Detail

HYE18M512160BF-7.5: Features: • 4 banks * 8 Mbit * 16 organization• Double-data-rate architecture : two data transfers per clock cycle• Bidirectional data strobe (DQS) is transmitted / received with d...

floor Price/Ceiling Price

Part Number:
HYE18M512160BF-7.5
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/3/27

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Product Details

Description



Features:

• 4 banks * 8 Mbit * 16 organization
• Double-data-rate architecture : two data transfers per clock cycle
• Bidirectional data strobe (DQS) is transmitted / received with data; to be used in capturing data at the receiver
• DQS is edge-aligned with data for READs and center-aligned with data for WRITEs
• Differential clock input (CK / CK)
• Commands entered on positive CK edge; data and mask data are referenced to both edges of DQS
• Four internal banks for concurrent operation
• Programmable CAS latency: 2 and 3
• Programmable burst length: 2, 4, 8 and 16
• Programmable drive strength (full, half, quarter)
• Auto refresh and self refresh modes
• 8192 refresh cycles / 64ms
• Auto precharge
• Commercial (0to +70) and Extended (-25 to +85) operating temperature range
• 60-ball Very Thin FBGA package (10.5 * 10.5 * 1.0 mm)
• RoHS Compliant Product1)



Specifications

Parameter Symbol Values Unit
min. max.
Power Supply Voltage VDD -0.3 2.7 V
Power Supply Voltage for Output Buffer VDDQ -0.3 2.7 V
Input Voltage VIN -0.3 VDDQ + 0.3 V
Output Voltage VOUT -0.3 VDDQ + 0.3 V
Operation Case Temperature Commercial TC 0 +70
  Extended TC -25 +85
Storage Temperature TSTG -55 +150
Power Dissipation PD 0.7 W
Short Circuit Output Current IOUT 50 mA

Attention: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.




Description

The HYE18M512160BF-7.5  is a high-speed CMOS, dynamic random-access memory containing 536,870,912 bits. It is internally configured as a quad-bank DRAM.

The HYE18M512160BF-7.5 uses a double-data-rate architecture to achieve high-speed operation. The doubledata- rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single READ or WRITE access for the DDR Mobile-RAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, onehalf clock cycle data transfers at the I/O pins.

The HYE18M512160BF-7.5 is especially designed for mobile applications. It operates from a 1.8V power supply. Power consumption in self refresh mode is drastically reduced by an On-Chip Temperature Sensor (OCTS); it can further be reduced by using the programmable Partial Array Self Refresh (PASR).

A conventional data-retaining Power-Down (PD) mode is available as well as a non-data-retaining Deep Power- Down (DPD) mode. For further power-savings the clock may be stopped during idle periods.

The HYE18M512160BF-7.5 is housed in a 60-ball very thin FBGA package. It is available in Commercial (0 to 70) and Extended (-25 to +85) temperature range.




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