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HYMP564R728-E3

Features: • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply• All inputs and outputs are compatible with SSTL_1.8 interface• 4 Bank architecture• Posted CAS• Programmable CAS Latency 3 , 4 , 5• OCD (Off-Chip Driver...

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SeekIC No. : 004369342 Detail

HYMP564R728-E3: Features: • JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply• All inputs and outputs are compatible with SSTL_1.8 interface• 4 Bank ...

HYMP564R728-E3 Data Sheet

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Part Number:
HYMP564R728-E3
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• JEDEC standard Double Data Rate2 Synchronous DRAMs (DDR2 SDRAMs) with 1.8V +/- 0.1V Power Supply
• All inputs and outputs are compatible with SSTL_1.8 interface
• 4 Bank architecture
• Posted CAS
• Programmable CAS Latency 3 , 4 , 5
• OCD (Off-Chip Driver Impedance Adjustment)
• ODT (On-Die Termination)
• Fully differential clock operations (CK & CK)
• Programmable Burst Length 4 / 8 with both sequential and interleave mode
• Auto refresh and self refresh supported
• 8192 refresh cycles / 64ms
• Serial presence detect with EEPROM
• DDR2 SDRAM Package: 60ball FBGA
• 133.35 x 30.00 mm form factor
• Lead-free Products are RoHS compliant


Specifications

Parameter
Symbol
Value
Unit
Note
Voltage on VDD pin relative to Vss
VDD
- 1.0 V ~ 2.3 V
V
1
Voltage on VDDL pin relative to Vss
VDDL
-0.5V ~ 2.3 V
V
1
Voltage on VDDQ pin relative to Vss
VDDQ
- 0.5 V ~ 2.3 V
V
1
Voltage on any pin relative to Vss
VIN,VOUT
- 0.5 V ~ 2.3 V
V
1
Storage Temperature
TSTG
-50 ~ +100
1
Storage Humidity(without condensation)
HSTG
5 to 95
%
1



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