Purchase IC42S16102, In-stock IC42S16102 From SeekIC.
Part Number: IC42S16102
Description: ICSI's 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved ...
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IC42S16102
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DataSheet
General Description
IC42S16102 General Description
ICSI's 16Mb Synchronous DRAM IC42S16102 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input.
IC42S16102 Maximum Ratings
| Symbol | Parameters | Rating | Unit |
| VDD MAX | Maximum Supply Voltage | 1.0 to +4.6 | V |
| VDDQ MAX | Maximum Supply Voltage for Output Buffer | 1.0 to +4.6 | V |
| VIN | Input Voltage | 1.0 to +4.6 | V |
| VOUT | Output Voltage | 1.0 to +4.6 | V |
| PD MAX | Allowable Power Dissipation | 1 | W |
| ICS | Output Shorted Current | 50 | mA |
| TOPR | Operating Temperature | 0 to +70 | |
| TSTG | Storage Temperature | 55 to +150 |
IC42S16102 Features
• Driver Strength for High capacitive bus loading
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400mil 50-pin TSOP-2 and 60ball(16M)
VF-BGA
• Pb(lead)-free package is available
• Clock frequency: 200, 166, 143 MHz
• Fully synchronous; all signals referenced to a
positive clock edge
• Two banks can be operated simultaneously and
independently
• Dual internal bank controlled by A11 (bank select)
• Single 3.3V power supply
• LVTTL interface
• Programmable burst length
(1, 2, 4, 8, full page)
• Programmable burst sequence:
Sequential/Interleave
• Auto refresh, self refresh
• 4096 refresh cycles every 64 ms
• Random column address every clock cycle
• Programmable CAS latency (2, 3 clocks)
• Burst read/write and burst read/single write
operations capability
• Burst termination by burst stop and precharge
command
• Byte controlled by LDQM and UDQM
• Package 400mil 50-pin TSOP-2 and 60ball(16M)
VF-BGA
• Pb(lead)-free package is available
IC42S16102 Connection Diagram
IC41C16100A
PDF/DataSheet Download
- Datasheet: IC41C16100A
- File Size: 237271 KB
- Manufacturer: ICSI [Integrated Circuit Solution Inc]
- Click here to Download
- ·IC41C16100A-50K
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
- ·IC41C16100A-50T
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
- ·IC41C16100A-60K
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
- ·IC41C16100A-60T
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
- ·IC41C16100AS
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
- ·IC41C16100AS-50K
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
- ·IC41C16100AS-50T
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
- ·IC41C16100AS-60K
- ICSI [Integrated Circuit Solution Inc]
- 1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE
- 237271 KB
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ICSI's 16Mb Synchronous DRAM IC42S16101 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of ...
IC42S16100
ICSI's 16Mb Synchronous DRAM IC42S16100 is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of ...
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