Features: • Access times of 55, 70, 100 ns• CMOS Low power operation:- 60 mW (typical) operation- 3 W (typical) standby• Low data retention voltage: 1.5V (min.)• Output Enable (OE) and Chip Enable(CE) inputs for ease in applications• TTL compatible inputs and outputs&...
IC62LV5128LL: Features: • Access times of 55, 70, 100 ns• CMOS Low power operation:- 60 mW (typical) operation- 3 W (typical) standby• Low data retention voltage: 1.5V (min.)• Output Enabl...
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Features: • High-speed access time: 35, 45, 55, 70 ns• Low active power: 450 mW (typic...
Features: • Access times of 55, 70, 100 ns• CMOS Low power operation: ICC=15mA (typica...
Symbol | Parameter | Value | Unit |
VTERM VCC TBIAS TSTG PT |
Terminal Voltage with Respect to GND Vcc related to GND Temperature Under Bias Storage Temperature Power Dissipation |
0.5 to Vcc + 0.5 0.3 to +4.0 40 to +85 65 to +150 1 |
V V °C °C W |
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The IC62LV5128LL is a low voltage, 524,288 words by 8 bits, CMOS SRAM. It is fabricated using ICSI's low voltage, six transistor (6T), CMOS technology. The device is targeted to satisfy the demands of the state-of-the-art technologies such as cell phones and pagers.
When CE of the IC62LV5128LL is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Additionally, easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE. The active LOW Write Enable ( WE) controls both writing and reading of the memory.
The IC62LV5128LL are available in 32-pin 8*20mm TSOP-1, 8*13.4mm TSOP-1 and 48-pin 6*8mm TFBGA.