ICS1523 General Description
ICS1523 Maximum Ratings
VDD, VDDA, VDDQ (measured to VSS) . . . . . . . . . . . . . . . . . 4.3 V
Digital Inputs . . . . . . . . . . .. . . . . . . . . . . . . . VSS - 0.3 V to 5.5 V
Analog Outputs . . . . .. . . . . . . . . . . . VSSA- 0.3 V to VDDA +0.3 V
Digital Outputs . . . . . . . . . . . . . . . . VSSQ -0.3 V to VDDQ +0.3 V
Storage Temperature . . . . . . . . . . . . . . . . . . . . . - 65 to +150
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Soldering Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260
ESD Susceptibility* . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . > 2 KV
(*Electrostatic-sensitive devices. Do not open or handle except in a static-free workstation.)
ICS1523 Features
· Pixel clock frequencies up to 250 MHz
· Very low jitter
· Dynamic Phase Adjust (DPA) for clock outputs
· Balanced PECL differential outputs
· Single-ended SSTL_3 clock outputs
· Double-buffered PLL/DPA control registers
· Independent software reset for PLL/DPA
· External or internal loop filter selection
· Uses 3.3Vdc. Inputs are 5V-tolerant.
· I2C-busTM serial interface can run at either low speed (100 kHz) or high speed (400 kHz).
· Lock detection
· 24-pin 300-mil SOIC package
ICS1523 Typical Application
·LCD monitors and video projectors
· Genlocking multiple video subsystems
· Frequency synthesis
ICS1523 Connection Diagram
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