ICS162835

The ICS162835 low voltage 18-bit register combines D-type latches and D-type flip-flops to allow data flow in ransparent, latched and clocked modes. Date flow is controlled by output-enable (OE#), latch enable (LE), and clock (CLK) inputs. The device operates in transparent mode when LE is held high. The device operates in clocked mode when LE is low and CLK is toggled. Data transfers from the inputs (A[18:1]) to outputs (Y[18:1]) on a positive edge transition of the clock. When OE# is low, the output state is enabled. When OE# is high, the output port is in a high impedance state.

The 18-bit registered buffer is designed to operate with a 3.0V to 4.6V supply voltage.

All inputs support operation with standard LVTTL interface levels. This includes data inputs, clock inputs and control inputs. Device outputs meet the requirements of the PC133 Registered DIMM specification. The device unctions as defined supports latched, registered and flow through modes of operations. The PC133 Specification requires only registered mode.

Package is a 56 thin shrink small-outline package as defined by JEDEC Publication, JEP95, MO-153.