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ICS527-01

Features: • Packaged as 28 pin SSOP (150 mil body)• Synchronizes fractional clocks rising edges• User determines the output frequency - no software needed• Slices frequency or period• SYNC pulse output indicates aligned edges• Input clock frequency of 600 kHz - ...

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SeekIC No. : 004370796 Detail

ICS527-01: Features: • Packaged as 28 pin SSOP (150 mil body)• Synchronizes fractional clocks rising edges• User determines the output frequency - no software needed• Slices frequency o...

ICS527-01 Data Sheet

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Part Number:
ICS527-01
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2024/5/18

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Product Details

Description



Features:

• Packaged as 28 pin SSOP (150 mil body)
• Synchronizes fractional clocks rising edges
• User determines the output frequency - no software needed
• Slices frequency or period
• SYNC pulse output indicates aligned edges
• Input clock frequency of 600 kHz - 200 MHz
• Output clock frequencies up to 160 MHz
• Very low jitter
• Duty cycle of 45/55 up to 160 MHz
• Operating voltage of 3.3 V (±10%)
• Pin selectable double drive strength
• Multiple outputs available when combined with Buffalo clock drivers
• Zero input to output skew
• Industrial temperature version available
 • Advanced, low power CMOS process


Pinout

Connection Diagram


Specifications

Parameter Conditions
Minimum
Typical
Maximum
Units
Supply Voltage, VDD Referenced to GND
7
V
Inputs Referenced to GND
-0.5
VDD+0.5
V
Clock Output Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature  
0
70
Soldering Temperature Max of 10 seconds
260
Storage temperature  
-65
150



Description

The ICS527-01 Clock Slicer™ is the most flexible way to generate an output clock from an input clock with zero skew. The user can easily configure the device to produce nearly any output clock that is multiplied or divided from the input clock. The part supports non-integer multiplications and divisions. A SYNC pulse indicates the rising clock edges that are aligned with zero skew. Using Phase-Locked Loop (PLL) techniques, the device accepts an input clock up to 200 MHz and produces an output clock up to 160 MHz.
 
The ICS527-01 aligns rising edges on ICLK and FBIN at a ratio determined by the reference and feedback dividers.

For configurable clocks that do not require zero delay, use the ICS525.




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