ICS601-01

Stresses above the ratings listed below can cause permanent damage to the ICS601-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range.

The ICS601-01 is a low-cost, low phase noise, high-performance clock synthesizer for applications which require low phase noise and low jitter. It is ICS' lowest phase noise multiplier, and also the lowest CMOS part in the industry. Using ICS' patented analong and digital Phase-Locked Loop (PLL) techniques, the chip accepts a 10 - 27 MHz crystal or clock input, and produces output clocks up to 156 MHz at 3.3 V.

This product of the ICS601-01 is intended for clock generation. It has low output jitter (variation in the output period), but input and output skew and jitter are not defined nor guaranteed. For applications which require definted input to output timing, use the ICS670-01.