Features: • Two differential LVPECL outputs• CLK input accepts the following input levels: LVCMOS or LVTTL levels• Output frequency: 122.88MHz (typical)• FemtoClock VCO frequency range: 490MHz - 680MHz• RMS phase jitter @ 122.88MHz, using a 19.2MHz crystal (1.875MHz t...
ICS843002I-72: Features: • Two differential LVPECL outputs• CLK input accepts the following input levels: LVCMOS or LVTTL levels• Output frequency: 122.88MHz (typical)• FemtoClock VCO frequ...
SeekIC Buyer Protection PLUS - newly updated for 2013!
268 Transactions
All payment methods are secure and covered by SeekIC Buyer Protection PLUS.
Features: • Accepts various HD and SD references including hsync,transport and pixel clock r...

Supply Voltage, VCC ...................4.6V
Inputs, VI ........... .....-0.5V to VCC + 0.5V
Outputs, IO (LVPECL)
Continuous Current................... 50mA
Surge Current .................. ...100mA
Package Thermal Impedance, JA ......37°C/W (0 mps)
Storage Temperature, TSTG.. .. .. .. -65°C to 150°C
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
The ICS843002I-72 is a member of the HiperClockS™ family of high performance clock solutions from IDT. The ICS843002I-72 is a PLL based synchronous clock generator that is optimized for WCDMA channel card applications where jitter attenuation and frequency translation is needed. The device contains two internal PLL stages that are cascaded in series. The first PLL stage uses a VCXO which is optimized to provide reference clock jitter attenuation and to be jitter tolerant, and to provide a stable reference clock for the second PLL stage. The second PLL stage provides additional frequency multiplication (x32), and it maintains low output jitter by using a low phase noise FemtoClock™ VCO. The device performance and the PLL multiplication ratios are optimized to support WCDMA applications. The VCXO requires the use of an external, inexpensive pullable crystal. VCXO PLL of the ICS843002I-72 uses external passive loop filter components which are used to optimize the PLL loop bandwidth and damping characteristics for the given application.
The ICS843002I-72 can accept a single-ended input. LOCK_DT reports the lock status of VCXO PLL loop. If the reference clock input is lost, it will set LOCK_DT to logic LOW.
Typical ICS843002I-72 configuration in WCDMA Systems:
• 19.2MHz pullable crystal
• Input Reference clock frequency: 3.84MHz
• Output clock frequency: 122.88MHz