ICS84320-01

POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as possibleto the power pins. If space allows, placement of the decoupling capacitor on the component side is preferred. This can reduce unwanted inductance between the decoupling capacitor and the power pin caused by the via. Maximize the power and ground pad sizes and number of vias apacitors. This can reduce the inductance between the power and ground planes and the component power and ground pins. The RC filter consisting of R7, C11, and C16 should be placed as close to the VCCA pin as possible.

CLOCK TRACES AND TERMINATION

Poor signal integrity can degrade the system performance or cause system failure. In synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. Any ringing on the rising or falling edge or excessive ring back can cause system failure. The shape of the trace and the trace delay might be restricted by the available space on the board and the component location. While routing the traces, the clock signal traces should be routed first and should be locked prior torouting other signal traces.

• The differential 50Ω output traces should have thesame length.
• Avoid sharp angles on the clock trace. Sharp angleturns cause the characteristic impedance to change onthe transmission lines.
• Keep the clock traces on the same layer. Whenever possible,avoid placing vias on the clock traces. Placementof vias on the traces can affect the trace characteristicimpedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces inparallel with the clock traces. If running parallel traces isunavoidable, allow a separation of at least three tracewidths between the differential clock trace and the othersignal trace.
• Make sure no other signal traces are routed between theclock trace pair.
• The matching termination resistors should be located asclose to the receiver input pins as possible.