Features: • 9 LVHSTL outputs• Selectable CLK, nCLK or LVPECL clock inputs• CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL• PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL• Maximum output frequency ...
ICS8521: Features: • 9 LVHSTL outputs• Selectable CLK, nCLK or LVPECL clock inputs• CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL•...
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Features: • Accepts various HD and SD references including hsync,transport and pixel clock r...
The ICS8521 is a low skew, 1-to-9 3.3V Differential- to-LVHSTL Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8521 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can ccept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulseson the outputs during asynchronous assertion/ assertion of the clock enable pin. Guaranteed output skew, part-to-part skew and crossover voltage characteristics make the ICS8521 ideal for today's most advanced applications, such as IA64 and static RAMs.