Features: •4 differential 3.3V LVPECL outputs
•Selectable CLK, nCLK or LVPECL clock inputs
•CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, HSTL, SSTL, HCSL
•PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
•Maximum output frequency up to 650MHz
•Translates any single-ended input signal to 3.3V LVPECL levels with resistor bias on nCLK input
•Output skew: 30ps (maximum)
•Part-to-part skew: 150ps (maximum)
•Propagation delay: 1.4ns (maximum)
•3.3V operating supply
•0 to 70ambient operating temperature
• Industrial temperature information available upon request
Pinout
SpecificationsSupply Voltage, VCCx 4.6V
Inputs, VI -0.5V to VCC + 0.5V
Outputs, VO -0.5V to VCC + 0.5V
Package Thermal Impedance, JA 73.2/W (0lfpm)
Storage Temperature, TSTG -65 to 150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these condition or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
DescriptionThe ICS8533-01 is a low skew, high performance 1-to-4 Differential-to-3.3V LVPECL fanout buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.
The ICS8533-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the ICS8533-01 ideal for those applications demanding well defined performance and repeatability.
ICS8533-01 Data Sheet
