ICS85411

Features:

• 2 differential LVDS outputs
• 1 differential CLK, nCLK clock input
• CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 650MHz
• Translates any single ended input signal to LVDS levels with resistor bias on nCLK input
• Output skew: 20ps (maximum)
• Part-to-part skew: 250ps (maximum)
• Additive phase jitter, RMS: 0.05ps (typical)
• Propagation delay: 2.5 ns (maximum)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request


Application

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 1 shows how the differential input can be wired to acceptsingle ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V  and R2/R1 = 0.609.

LVDS DRIVER TERMINATION

A general LVDS interface is shown in Figure 2. In a 100 differential transmission line environment, LVDS drivers require a matched load termination of 100 across near the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the un-used outputs.

DIFFERENTIAL CLOCK INPUT INTERFACE

The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 3A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.

Pinout

The ICS85411 is a low skew, high performance 1-to-2 Differential-to-LVDS Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.The ICS85411 is characterized to operate from a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS85411 ideal for those clock distribution applications demanding well defined performance and repeatability.


Specifications

Supply Voltage, VDD 4.6V
Inputs, VI -0.5V to VDD + 0.5V
Outputs, IO
Continuous Current 10mA
Surge Current 15mA
Package Thermal Impedance, JA 112.7°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C


Description

The ICS85411 is a low skew, high performance 1-to-2 Differential-to-LVDS Fanout Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The CLK, nCLK pair can accept most standard differential input levels.The ICS85411 is characterized to operate from a 3.3V power supply. Guaranteed output and
part-to-part skew characteristics make the ICS85411 ideal for those clock distribution applications demanding
well defined performance and repeatability.