ICS87004

Features:

* 4 LVCMOS/LVTTL outputs, 7? typical output impedance
* Selectable CLK0, nCLK0 or CLK1, nCLK1 clock inputs
* CLKx, nCLKx pairs can accept the following differential
   input levels:  LVPECL, LVDS, LVHSTL, HCSL, SSTL
* Internal bias on nCLK0 and nCLK1 to support
   LVCMOS/LVTTL levels on CLK0 and CLK1 inputs
* Output frequency range: 15.625MHz to 250MHz
* Input frequency range: 15.625MHz to 250MHz
* VCO range: 250MHz to 500MHz
* External feedback for "zero delay" clock regeneration
   with configurable frequencies
* Programmable dividers allow for the following output-to-input
   frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
* Fully integrated PLL
* Cycle-to-cycle jitter:  45ps (maximum)
* Output skew:  45ps (maximum)
* Static phase offset:  50 ± 125ps (3.3V ± 5%)
* Full 3.3V or 2.5V operating supply
* 5V tolerant inputs
* Lead-Free package available
* Industrial temperature information available upon request


Pinout




Specifications

Supply Voltage, V_DD                                                                 4.6V
Inputs, V_I                                                         -0.5V to V_DD + 0.5 V 
Outputs, V_O                                                   -0.5V  to V_DDO + 0.5V 
Package Thermal Impedance, _JA                         70°C/W (0 lfpm)
Storage Temperature, T_STG                                  -65°C to 150°C



Description

The ICS87004 is a highly versatile 1:4 Differential-to-LVCMOS/LVTTL Clock Generator and a mem-ber of the HiPerClockS(TM)  family of High Perfor- mance Clock Solutions from ICS. The ICS87004 has two selectable clock inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs can accept most standard differential input levels. Internal bias on the nCLK0 and nCLK1 inputs allows the CLK0 and CLK1 inputs to accept LVCMOS/LVTTL.

The ICS87004 has a fully integrated PLL and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625MHz to 250MHz. The refer- ence divider, feedback divider and output divider are each programmable, thereby allowing for the following output-to- input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The exter- nal feedback allows the device to achieve "zero delay" between the input clock and the output clocks. The PLL_SEL pin can be used to bypass the PLL for system test and debug purposes. In bypass mode, the reference clock of the ICS87004 is routed around the PLL and into the internal output dividers.