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Part Number: ICS8701
Description: The ICS8701 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ family of Hig...
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ICS8701
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DataSheet
General Description
ICS8701 General Description
The ICS8701 is a low skew, ÷1, ÷2 Clock Generator and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The low impedance LVCMOS outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 20 to 40 by utilizing the ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The bank enable inputs, BANK_EN0:1, support enabling and disabling each bank of outputs individually. The master reset input, nMR/ OE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs.
The ICS8701 is characterized at 3.3V and mixed 3.3V input supply, and 2.5V output supply operating modes. Guaranteed bank, output and part-to-part skew characteristics make the ICS8701 ideal for those clock distribution applications demanding well defined performance and repeatability.
ICS8701 Maximum Ratings
Supply Voltage, VDDx ..................................4.6V
Inputs, VI ................................-0.5V to VDD + 0.5V
Outputs, VO ..............................-0.5V to VDDO + 0.5V
Package Thermal Impedance, JA ....................47.9°C/W (0lfpm)
Storage Temperature, TSTG........................ -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS8701 Features
• 20 LVCMOS outputs, 7 typical output impedance
• 1 LVCMOS clock input
• Maximum output frequency up to 250MHz
• Bank enable logic allows unused banks to be disabled in reduced fanout applications
• Output skew: 250ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 200ps (maximum)
• Multiple frequency skew: 300ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• 1 LVCMOS clock input
• Maximum output frequency up to 250MHz
• Bank enable logic allows unused banks to be disabled in reduced fanout applications
• Output skew: 250ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 200ps (maximum)
• Multiple frequency skew: 300ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
ICS8701 Connection Diagram
ICS8701-01
PDF/DataSheet Download
- Datasheet: ICS8701-01
- File Size: 215046 KB
- Manufacturer: ICST [Integrated Circuit Systems]
- Click here to Download
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