Features: •2 divide by 1 differential 3.3V LVPECL outputs;2 divide by 2 differential 3.3V LVPECL outputs•Selectable CLK, nCLK or LVPECL clock inputs•CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL•PCLK, nPCLK supports the ...
ICS8737-11: Features: •2 divide by 1 differential 3.3V LVPECL outputs;2 divide by 2 differential 3.3V LVPECL outputs•Selectable CLK, nCLK or LVPECL clock inputs•CLK, nCLK pair can accept the f...
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Features: • Accepts various HD and SD references including hsync,transport and pixel clock r...

The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/ Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differ-ential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the ICS8737-11 ideal for clock distribution applications demanding well defined performance and repeatability.