ICS8737-11

Features: •2 divide by 1 differential 3.3V LVPECL outputs;2 divide by 2 differential 3.3V LVPECL outputs•Selectable CLK, nCLK or LVPECL clock inputs•CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL•PCLK, nPCLK supports the ...

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SeekIC No. : 004371094 Detail

ICS8737-11: Features: •2 divide by 1 differential 3.3V LVPECL outputs;2 divide by 2 differential 3.3V LVPECL outputs•Selectable CLK, nCLK or LVPECL clock inputs•CLK, nCLK pair can accept the f...

floor Price/Ceiling Price

Part Number:
ICS8737-11
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/4

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Product Details

Description



Features:

•2 divide by 1 differential 3.3V LVPECL outputs;2 divide by 2 differential 3.3V LVPECL outputs
•Selectable CLK, nCLK or LVPECL clock inputs
•CLK, nCLK pair can accept the following differential input levels:  LVDS, LVPECL, LVHSTL, SSTL, HCSL
•PCLK, nPCLK supports the following input types:LVPECL, CML, SSTL
•Maximum output frequency up to 650MHz
•Translates any single ended input signal (LVCMOS, LVTTL,GTL) to LVPECL levels with resistor bias on nCLK input
•Output skew:  60ps (maximum)
•Part-to-part skew:  200ps (maximum)
•Bank skew:Bank A - 20ps (maximum),Bank B - 35ps (maximum)
•Propagation delay:  1.7ns (maximum)
•3.3V operating supply
•0°C to 70°C ambient operating temperature
•Industrial temperature information available upon request



Pinout

  Connection Diagram


Specifications

Supply Voltage, VCC                                             4.6V
Inputs, VI                                    -0.5V  to VCC + 0.5V
Outputs, VO                                  -0.5V to VCC+ 0.5V
Package Thermal Impedance, JA  73.2°C/W (0lfpm)
Storage Temperature, TSTG            -65°C to 150°C



Description

The ICS8737-11 is a low skew, high performance Differential-to-3.3V LVPECL Clock Generator/ Divider and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8737-11 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differ-ential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels.The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin.

Guaranteed output and part-to-part skew characteristics make the ICS8737-11 ideal for clock distribution applications demanding well defined performance and repeatability.




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