ICS87931I

Features: • Fully integrated PLL• 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock for redundant clock applications• Maximum output frequency: 150MHz• VCO range: 220MHz to 480MHz• External feedb...

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SeekIC No. : 004371102 Detail

ICS87931I: Features: • Fully integrated PLL• 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock for redundant clock applicati...

floor Price/Ceiling Price

Part Number:
ICS87931I
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Upload time: 2025/12/25

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Product Details

Description



Features:

• Fully integrated PLL
• 6 LVCMOS/LVTTL outputs, 7Ω typical output impedance
• Selectable differential CLK0, nCLK0 or LVCMOS/LVTTL clock for redundant clock applications
• Maximum output frequency: 150MHz
• VCO range: 220MHz to 480MHz
• External feedback for "zero delay" clock regeneration
• Output skew, Same Frequency: 300ps (maximum)
• Output skew, Different Frequency: 400ps (maximum)
• Cycle-to-cycle jitter: 100ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Pin compatible with MPC931



Pinout

  Connection Diagram


Specifications

Supply Voltage, VDD..................................................... 4.6V
Inputs, VI ..........................................-0.5V to VDDA + 0.5 V
Outputs, VO....................................... -0.5V to VDDO + 0.5V
Package Thermal Impedance, JA .........47.9°C/W (0 lfpm)
Storage Temperature, TSTG....................  -65°C to 150°C



Description

The ICS87931I is a low voltage, low skew LVCMOS/LVTTL Clock Multiplier/Zero Delay Buffer and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. With output frequencies up to 150MHz, the ICS87931I is targeted for high performance clock applications. Along with a fully integrated PLL, the ICS87931I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay". Selectable clock inputs, CLK1 and differential CLK0, nCLK0 support redundant clock applications. The CLK_SEL input determines which reference clock is used.

The output divider values of Bank A, B and C are controlled by the DIV_SELA, DIV_SELB and DIV_SELC, respectively. For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When LOW, the nMR input resets the internal dividers and forces the outputs to the high impedance state.

The effective fanout of the ICS87931I can be increased to 12 by utilizing the ability of each output to drive two series terminated transmission lines.




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