ICS889831

Features:

• 4 differential LVPECL/ECL outputs
• IN, nIN pair can accept the following differential input levels:
LVPECL, LVDS, CML, SSTL
• 50 internal input termination to VT
• Maximum output frequency: > 2.1GHz
• Output skew: 30ps (maximum)
• Part-to-part skew: 185ps (maximum)
• Additive phase jitter, RMS: 0.27ps (typical)
• Propagation delay: 570ps (maximum)
• LVPECL mode operating voltage supply range:
V_CC = 2.5V ± 5%, 3.3V ± 5%, V_EE = 0V
• ECL mode operating voltage supply range:
V_CC = 0V, V_EE = -3.3V ± 5%, 2.5V ± 5%
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant


Pinout




Specifications

Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Input Current, IN, nIN VT Current, IVT Input Sink/Source, IREF_AC Operating Temperature Range, TA Storage Temperature, TSTG Package Thermal Impedance, JA (Junction-to-Ambient)

4.6V (LVPECL mode, VEE = 0) -4.6V (ECL mode, VCC = 0) -0.5V to VCC + 0.5 V 0.5V to VEE - 0.5V 50mA 100mA ±50mA ±100mA ± 0.5mA -40°C to +85°C -65°C to 150°C 51.5°C/W (0 lfpm)

Description

The ICS889831 is a high speed 1-to-4 Differentialto- LVPECL/ECL Fanout Buffer and is a member of the HiPerClockS™ family of high performance clock solutions from ICS. The ICS889831 is optimized for high speed and very low output knew, making it suitable for use in demanding applications such as SONET, 1 Gigabit and 10 Gigabit Ethernet, and Fibre Channel. The internally terminated differential input and VREF_AC pin allow other differential signal families such as LVDS, LVHSTL and CML to be easily interfaced to the input with minimal use of external components. The device also has an output enable pin which may be useful for system test and debug purposes. The ICS889831 is packaged in a small 3mm x 3mm 16-pin VFQFN package which makes it ideal
for use in space-constrained applications.