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ICS9112-16

Features: • Zero input - output delay• Frequency range 25 - 133 MHz (3.3V)• High loop filter bandwidth ideal for Spread Spectrum applications.• Less than 200 ps Jitter between outputs• Skew controlled outputs• Skew less than 250 ps between outputs• Availab...

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SeekIC No. : 004371113 Detail

ICS9112-16: Features: • Zero input - output delay• Frequency range 25 - 133 MHz (3.3V)• High loop filter bandwidth ideal for Spread Spectrum applications.• Less than 200 ps Jitter betwee...

ICS9112-16 Data Sheet

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Part Number:
ICS9112-16
Supply Ability:
5000

Price Break

  • Qty
  • 1~5000
  • Unit Price
  • Negotiable
  • Processing time
  • 15 Days
Total Cost: $ 0.00

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Product Details

Description



Features:

• Zero input - output delay
• Frequency range 25 - 133 MHz (3.3V)
• High loop filter bandwidth ideal for Spread Spectrum applications.
• Less than 200 ps Jitter between outputs
• Skew controlled outputs
• Skew less than 250 ps between outputs
• Available in 8 pin 150 mil SOIC or 173 mil TSSOP package.
• 3.3V ±10% operation


Pinout

Connection Diagram


Specifications

Supply Voltage ..............................7.0 V
Logic Inputs  ....................GND 0.5 V to VDD +0.5 V
Ambient Operating Temperature................0°C to +70°C
Storage Temperature ...................65°C to +150°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.


Description

The ICS9112-16 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology toalign, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in PC systems operating at speeds from 25 to 133 MHz.

ICS9112-16 is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer.

The ICS9112-16 comes in an eight pin 150 mil SOIC or 173 mil TSSOP package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition.




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