ICS91305

·Zero input - output delay
·Frequency range 10 - 133 MHz (3.3V)
·5V tolerant input REF
·High loop filter bandwidth ideal for Spread Spectrum applications.
·Less than 200 ps Jitter between outputs
·Skew controlled outputs
·Skew less than 250 ps between outputs
·Available in 8 pin 150 mil SOIC & 173 mil TSSOP packages
·3.3V ±10% operation

Supply Voltage ......................................................................7.0 V
Logic Inputs (Except REF) ...................GND 0.5 V to VDD + 0.5 V
Logic Input REF .................................. GND 0.5 V to GND + 5.5 V
Ambient Operating Temperature ............................... 0 to +70
Storage Temperature ......................................... 65 to +150

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

The ICS91305 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal. It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz. ICS91305 is a zero delay buffer that provides synchronization between the input and output.

The synchronization of the ICS91305 is established via CLKOUT feed back to the input of the PLL. Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer.

The ICS91305 comes in an eight pin 150 mil SOIC package. It has five output clocks. In the absence of REF input, will be in the power down mode. In this mode, the PLL is turned off and the output buffers are pulled low. Power down mode provides the lowest power consumption for a standby condition.