ICS91305I

Supply Voltage. . . . . . . . . . . . . . . .  . . . . . . . . . . . . . . . 7.0 V
Logic Inputs (Except REF). . . . . . . . .GND -0.5 V_DD to + 0.5 V
Logic Input REF. . . . . . . . . . . . . . . . GND -0.5 V to GND + 5.5
Ambient Operating Temperature. . . . . . . . . .  -40 to +85
Storage Temperature. . . . . . . . . . . .. . . . . .  -65 to +150

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.

The ICS91305I is a high performance, low skew, low jitter clock driver.  It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF input with the CLKOUT signal.  It is designed to distribute high speed clocks in communication systems operating at speeds from 10 to 133 MHz.

ICS91305I is a zero delay buffer that provides synchronization between the input and output. The synchronization is established via CLKOUT feed back to the input of the PLL.  Since the skew between the input and output is less than +/- 350 pS, the part acts as a zero delay buffer.

The ICS91305I comes in an eight pin 150 mil SOIC package.  It has five output clocks.  In the absence of REF input, will be in the power down mode.  In this mode, the PLL is turned off and the output buffers are pulled low.Power down mode provides the lowest power consumption for a standby condition.