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Part Number: ICS9148-11
Description: The ICS9148-11 generates all clocks required for high speed RISC or CISC microprocessor systems such a...
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ICS9148-11
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DataSheet
General Description
ICS9148-11 General Description
The ICS9148-11 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro. An output enable pin is provided for testability. MODE allows power management functions: CPU_STOP#, PCI_STOP# & PWR_DWN#.
High drive BCLK outputs typically provide greater than 1 V/ns slew rate into 30 pF loads. PCLK outputs typically provide better than 1V/ ns slew rate into 20 pF loads while maintaining 50±5% duty cycle. The REF clock outputs typically provide better than 0.5V/ns slew rates.
ICS9148-11 Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . GND - 0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS9148-11 Features
· Generates four processor, six bus, one 14.31818MHz and 12 SDRAM clocks.
· Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on BUS clocks.
· CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
· Test clock mode eases system design
· Custom configurations available
· VDD(1:3) - 3.3V ±10% (inputs 5V tolerant w/series R )
· VDDL(1:2) - 2.5V or 3.3V ±5%
· PC serial configuration interface
· Power Management Control Input pins
· 48-pin SSOP package
· Synchronous clocks skew matched to 250ps window on CPU, SDRAM and 500ps window on BUS clocks.
· CPUCLKs to BUS clocks skew 1-4 ns (CPU early)
· Test clock mode eases system design
· Custom configurations available
· VDD(1:3) - 3.3V ±10% (inputs 5V tolerant w/series R )
· VDDL(1:2) - 2.5V or 3.3V ±5%
· PC serial configuration interface
· Power Management Control Input pins
· 48-pin SSOP package
ICS9148-11 Connection Diagram
ICS9148-11
PDF/DataSheet Download
- Datasheet: ICS9148-11
- File Size: 594484 KB
- Manufacturer: ICST [Integrated Circuit Systems]
- Click here to Download
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