ICS9169C-27

Features:

·Twelve selectable CPU clocks operate up to 83.3MHz
·Maximum CPU jitter of ± 200ps
·Six BUS clocks support sync or async bus operation
·250ps skew window for CPU outputs, 500ps skew window for BUS outputs
·CPU clocks BUS clocks skew 1-4ns (CPU early)
·Integrated buffer outputs drive up to 30pF loads
·3.0V - 3.7V supply range, CPU(1:6) outputs 2.5V(2.375- 2.62V) VDD option
·32-pin SOIC/SOJ package
·Logic inputs latched at Power-On for frequency selection saving pins as Input/Output
·48 MHz clock for USB support and 24 MHz clock for FD.

 

Pinout




Specifications

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND -0.5 V to V_DD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . 0 to +70
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65 to +150 


Description

The ICS9169C-27 is a low-cost frequency generator designed specifically for Pentium based chip set systems. The integrated buffer minimizes skew and provides all the clocks required. A 14.318 MHz XTAL oscillator provides the reference clock to generate standard Pentium frequencies. The CPU clock makes gradual frequency transitions without violating the PLL timing of internal microprocessor clock multipliers.

Twelve CPU clock outputs of the ICS9169C-27 provide sufficient clocks for the CPU, chip set, memory and up to two DIMM connectors (with four clocks to each DIMM). Either synchronous(CPU/2) or asynchronous (32 MHz) PCI bus operation can be selected by latching data on the BSEL input.