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Part Number: IDT2308A

 

 

 

 

Description: The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-sp...


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IDT2308A General Description


The IDT2308A is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications.

The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

The IDT2308A has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT2308A enters power down. In this mode, the device will draw less than 12A for Commercial Temperature range and less than 25A for Industrial temperature range, and the outputs are tri-stated. The IDT2308A is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.)

The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs.

The IDT2308A is characterized for both Industrial and Commercial operation.

IDT2308A Maximum Ratings

Symbol Rating
Max.
Unit
VDD Supply Voltage Range
0.5 to +4.6
V
VI (2) Input Voltage Range (REF)
0.5 to +5.5
V
VI Input Voltage Range
except REF)
0.5 to
VDD+0.5
V
IIK (VI < 0) Input Clamp Current
50
mA
IO
(VO = 0 to VDD)
Continuous Output Current
±50
mA
VDD or GND Continuous Current
±100
mA
TA = 55°C
(in still air)(3)
Maximum Power Dissipation
0.7
W
TSTG Storage Temperature Range
65 to +150
Operating
Temperature
Commercial Temperature
Range
0 to +70
Operating
Temperature
Industrial Temperature
Range
-40 to +85

IDT2308A Features

• Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
IDT2308A-1 1x
IDT2308A-2 1x, 2x
IDT2308A-3 2x, 4x
IDT2308A-4 2x
IDT2308A-1H and -2H for High Drive
• No external RC network required
• Operates at 3.3V VDD
• Available in SOIC and TSSOP packages

IDT2308A Typical Application

• SDRAM
• Telecom
• Datacom
• PC Motherboards/Workstations
• Critical Path Delay Designs

IDT2308A Connection Diagram

IDT2308A  Connection Diagram

IDT2308A datasheet

IDT 79R3081
PDF/DataSheet Download

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