IDT23S08T

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
  cause permanent damage to the device. This is a stress rating only and functional
  operation of the device at these or any other conditions above those indicated in the
  operational sections of this specification is not implied. Exposure to absolute maximum
  rating conditions for extended periods may affect reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output
  clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature
  of 150°C and a board trace length of 750 mils

The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz.

The IDT23S08T has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT23S08T enters power down. In this mode, the device will draw less than 12A, and the outputs are tri-stated.

The IDT23S08T is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.)

The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT23S08T is characterized for Commercial operation